this post was submitted on 17 Jul 2025
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RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

riscv.org

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Milk-V Titan (RISC-V MINI-ITX, powered by UltraRISC UR-DP1000) (milkv.io)
submitted 2 weeks ago by JRepin@lemmy.ml to c/riscv@lemmy.ml
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8 High-Performance RISC-V Cores UR-CP100 (up to 2.0GHz)

  • 1 Cluster (4x UR-CP100 cores) sharing 4MB, total 8MB
  • System-level cache: 16MB shared by 2 cluster (8 cores)

The Most Powerful RISC-V Core in Mass Production to Date - UR-CP100 (RV64GCBHX)

  • 64-bit out-of-order 4-issue superscalar microarchitecture
  • SPECCPU2006 single-core INT@10.4/GHz
  • SPECCPU2006 single-core FP@12/GHz
  • UltraRISC proprietary high-performance "X" instruction set extension

Compliant with RISC-V International Foundation Standards

  • Fully Compliant with RVA22
  • Compliant with RVA23* (excluding "V" extension)

Supports DDR4 Memory Stick, Up to 64GB

  • Compatible with standard PC-grade memory stick (UDIMM)
  • Supports standard DDR4 JEDEC JESD79-4A protocol
  • Supports maximum speed of 3200MT/s
  • Supports ECC

Supports UEFI Boot

  • Supports ACPI, CPPC, SMBIOS
  • Standardized boot support
  • Native ISO file mounting
  • More flexible boot options
  • Enhanced security

Supports Commodity NVMe SSDs (PCIe Gen4 4-lane)

Supports High-Speed USB3 5Gbps

Onboard Full-Size PCIe Connector with PCIe Gen4 16-lane

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[–] toothbrush@lemmy.blahaj.zone 5 points 2 weeks ago

I assume with "V" they mean vector? Then it wont, because RVA23 compliance requires the vector extensions. One cant just say "we are nearly compliant!" But apparently they just did.