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Raspberry Pi 5 Benchmarks: Significantly Better Performance, Improved I/O (www.phoronix.com)

submitted 1 year ago by d3Xt3r@lemmy.nz to c/technology@lemmy.world

122 comments fedilink hide all child comments

Four years after the Raspberry Pi 4 shipped, today the Raspberry Pi 5 is launching with a much improved SoC leading to significant performance gains.

The Raspberry Pi 5 is designed to deliver a 2~3x performance improvement over the Raspberry Pi 4. The Raspberry Pi 5 features a quad-core Cortex-A76 processor that clocks up to 2.4GHz, compared to the four Cortex-A72 cores found in the Raspberry Pi 4 that only clocked up to 1.8GHz. The graphics are also much-improved with now having an 800MHz VideoCore VII graphics processor over the VideoCore VI graphics with the Raspberry Pi 4. The Raspberry Pi 5 is capable of driving two 4K @ 60Hz displays and features 4K @ 60 HEVC decode hardware capabilities.

Also interesting with the Raspberry Pi 5 is that it features in-house silicon in the form of the RP1 "southbridge" used for much of the board's I/O capabilities. This southbridge should yield faster USB I/O along with other I/O bandwidth upgrades like a doubling of the peak SD card performance. The Raspberry Pi 5 also features a single-lane PCI Express 2.0 interface for improved connectivity.

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[–] 9point6@lemmy.world 51 points 1 year ago* (last edited 1 year ago) (3 children)

Honestly, given the improvement of every other capability in the boards over the years, it's really mad we don't have an m.2 slot as an option. Even if they ended up having to create a slightly more expensive SKU (which they seem to have no issues with given the memory options for the Pi4), I don't think anyone would complain

Edit: apparently there's gonna be an M.2 HAT, so that's something at least, would prefer an option to have it on the board and the GPIO header available for something else

[–] cooopsspace@infosec.pub 35 points 1 year ago* (last edited 1 year ago) (1 children)

The single least reliable part of a raspberry pi is the storage. Always has been.

I don't even need more professor performance, because the storage performance is the worst part.

[–] ngons@feddit.nu 39 points 1 year ago (1 children)

The professor really is what sets this device apart from competition

[–] Pons_Aelius@kbin.social 14 points 1 year ago (2 children)

The professor...

Are we talking Gilligan's Island or Futurama?

[–] ngons@feddit.nu 7 points 1 year ago

Not sure, but i couldn’t help myself :D

[–] Droechai@lemm.ee 3 points 1 year ago (1 children)

Professor Calculus from Tintin

[–] CosmicCleric@lemmy.world 2 points 1 year ago

Professor Calculus from Tintin

Talk about setting the Wayback Machine on high..

[–] mosiacmango@lemm.ee 7 points 1 year ago (1 children)

Likely an issue with the pci express lane not being able to handle nvme and everything else.

[–] 9point6@lemmy.world 14 points 1 year ago (1 children)

I thought that might be the case too, but the launch page has a line that suggests an M.2 HAT will use the new PCI-E interface, so it does make you wonder why they couldn't include the connector on the board. Might just be me, but I feel like people have been asking for this since they gave up asking for a SATA connector

[–] jollyrogue@lemmy.ml 3 points 1 year ago

Probably form factor reasons. The RPi5 doesn’t break the form the RPi3(?) set.

[–] thehatfox@lemmy.world 6 points 1 year ago

Looking at photos of the Pi5 board, the PCIe pins are a separate ribbon connector. I am guessing the M2 hat will just use the GPIO pins for power and hardware detection, and pass the others through.

I agree it would be have been useful to have an M2 slot (or maybe eMMC connector) integrated indirectly to the board. Other similar SBCs have done so. Perhaps the Pi designers were concerned about board space or thermal considerations. I imagine they want to keep the form factor as similar as possible each version, so they maybe can’t make drastic changes to the board layout.